Voltage translator circuits typically incorporate a latch because the cross-coupled logic gates in a latch ideally do not consume any current unless they are switching states. For example, consider a prior art voltage translator 100 shown in FIG. 1. Voltage translator circuit 100 translates an input voltage signal Vin_p and its complement Vin_n into corresponding output voltage signals Vout_p and its complement Vout_n, respectively. The input voltage signals are in a low voltage domain whereas the output signals are in a high voltage domain.
To distinguish between the logic states in the different voltage domains, lower case letters (logic low and logic high) will refer herein to the logic states in the low voltage domain. Thus, one of the input voltage signals Vin_p and Vin_n will be logic high whereas the other will be logic low. Conversely, the logic states in the high voltage domain will be capitalized (Logic High and Logic Low). One of the output voltage signals Vout_p and Vout_n will thus Logic High whereas the other will be Logic Low. Given these conventions, the problems with the switching speed of conventional latching voltage translator circuits such as circuit 100 will now be described.
The cross-coupled logic gates in voltage translator circuit 100 comprise a pair of NAND gates 105. The output nodes of NAND gates 105 are designated by the letter z. Each NAND gate 105 has a pair of input nodes a and b. Because gates 105 are cross-coupled, the input node b for each gate 105 is tied to the output node z for the opposing gate. To distinguish between NAND gates 105, one is deemed as the positive gate XMP since its output node z drives a positive internal latching node Vlatch_p. A remaining NAND gate 105 is designated as the negative gate XMN since its output node z drives a complementary internal latching node Vlatch_n. An inverter 130 inverts the logic state of node Vlatch_n to form output voltage signal Vout_p. Similarly, an inverter 135 inverts the logic state of node Vlatch_p to form complementary output voltage signal Vout_n.
Input voltage signal Vin_p drives the gate of an NMOS transistor 110 that has its source coupled to ground (Vss1 or logic low) and its drain coupled to the drain of a diode-connected PMOS transistor 120. The source of diode-connected PMOS transistor 120 couples to high voltage supply Vdd2 (the Logic High voltage value) whereas its gate/drain couples to the a input for positive gate XMP. Transistors 110 and 120 thus form an input path for input voltage signal Vin_p to positive gate XMP. Complementary input voltage signal Vin_n drives the a input of negative NAND gate XMN through a corresponding input path that comprises NMOS transistor 115 and a diode-connected PMOS transistor 125.
As shown in FIG. 2, each NAND gate 105 includes an inverter formed by a PMOS transistor 215 and an NMOS transistor 205. The b input for NAND gate 105 drives the gates of transistors 205 and 215 whereas the a input for NAND gate 105 drives the gates of a PMOS transistor 210 and an NMOS transistor 200. The source of NMOS transistor 200 is tied to an intermediate voltage supply Vss2 (voltage Vss2 being the Logic Low value). Referring again to FIG. 1, if input voltage signal Vin_p is logic low then this value is translated into a Logic Low value for output signal Vout_p. The z output of positive NAND gate XMP will thus be Logic Low as well whereas the z output of negative NAND gate XMN will be Logic High.
If input signal Vin_p is then switched to logic high, positive NAND gate XMP must then change states such that its inverter output z must flip from Logic Low to Logic High. To do so, PMOS transistor 210 in NAND gate XMP must switch from off to on whereas its NMOS transistor 200 must switch from on to off. One can see that the voltage for input node a to positive NAND gate XMP must fall to approximately (Vdd2−Vss2)/2 to switch PMOS transistor 210 on and switch off NMOS transistor 200. Such a switch involves three delays: There is a first delay for NMOS transistor 110 to turn on when input signal Vin_p switches to logic high. A second delay is incurred in getting diode-connected PMOS transistor 120 to turn on. Finally, there is the third delay to get PMOS transistor 210 to switch on and to get NMOS transistor 200 to switch off.
Analogous delays occur if complementary input voltage signal Vin_n is switched from logic low to logic high. In that case, there is the initial delay to get NMOS transistor 115 to turn on, which is then followed by the delay to get diode-connected PMOS transistor 125 to turn on. Finally, there is the delay required for PMOS transistor 210 in NAND gate XMN to switch on and for NMOS transistor 200 to switch off. One can thus see that regardless of the particular logic states for the input voltage signals Vin_p and Vin_n, the three delays discussed above will thus always be incurred whenever the input voltage signals switch logic states. Therefore, a conventional latching voltage translator requires substantial time to switch states such as 500 picoseconds. Not only is the delay problematic, but substantial current is consumed during these extended switching intervals.
Accordingly, there is a need in the art for improved voltage translators with faster switching times and correspondingly low power consumption.